The invention relates to point-to-point signaling, such as that optimally used to communicate data at high-speeds between adjacent function units in a digital system. More particularly, the invention relates to full-duplex point-to-point signaling.
The need for high-performance communication between chip components of computer elements continues to increase data transmission frequencies. The recent rise of clock forwarding techniques has enabled the signaling of multiple data bits per clock period. This means that edge rates may regularly be several times the clock rate. The increase in fast data edges has also increased reflected noise. Consequently, the signal transmission characteristics of chip, module, and connector signal paths have become more critical. Interconnect signaling circuits must support signal integrity at frequencies comparable to the edge rates for the data being communicated and in the presence of significant reflected noise. What is needed is a data receiver for full-duplex point-to-point data transmission that exhibits good signal integrity while operating over very reflective transmission lines and in an environment with large on-chip ground and power-supply noise.
Prior-art data receiver designs have required the use of expensive analog differential amplifiers having large numbers of components, large size, high power, and with stringent Common Mode design requirements. Thus what is further needed is a data receiver with a fewer components, smaller size, lower power, and is easier to implement than designs requiring differential amplifiers.
A data receiver for full-duplex point-to-point data transmission is described includes an integrating sampling capacitor, pass-gates having particular resistive characteristics, an auto-zero inverter, and a set of inverter stages for squaring the output of the inverter. These components are used to implement sampled-data methods and structures that integrate the channel signaling voltage and perform received data extraction from the full-duplex channel signal. The sampled-data receiver exhibits good signal integrity while operating over very reflective transmission lines and in an environment with large on-chip ground and power-supply noise. The sampled-data receiver also uses fewer components, is smaller, has lower power, and is easier to implement than continuous-time prior-art designs that require analog differential amplifiers with stringent Common Mode signal requirements.